Strain engineering using stress nitride overlayers is commonly employed in CMOS technologies for enhancing channel carrier mobility in short channel devices. Performance of NFETS may be improved by applying a stressed nitride layer exhibiting high tensile stress for increasing electron mobility. Similarly, PFET performance may be improved by applying a stressed layer exhibiting high compressive stress for increasing hole mobility. However, for long channel devices, the same stress layers degrade circuit performance, and, therefore, are undesirable. Unfortunately, since all designs use a combination of devices and structures having different dimensions, such as thick gate oxide or dual gate oxide (DGO) devices, analog devices (AVT), and passive devices, such as fuses, diffusion resistors, or poly resistors, elimination of stressed overlayers would degrade the performance of the short channel devices.
A need therefore exists for methodology enabling optimization of the application of stress overlayers to target the electrical behavior of semiconductor devices.